1. Field of the Invention
The present invention relates to a semiconductor device, such as a Large Scale Integrated Circuit (LSI) or the like, and a method for manufacturing the same.
2. Description of the Related Art
In recent years, attention has focused on a process of forming a fully silicided (FUSI) electrode structure as a next-generation semiconductor process.
A conventional method of forming the FUSI electrode structure will be described with reference to FIG. 32 (see Japanese Unexamined Patent Application Publication No. 2006-261282 (particularly, FIG. 1)). Initially, a polysilicon gate electrode is formed on a semiconductor substrate 1 with a gate oxide film 2 interposed therebetween, and thereafter, sidewall insulating films 4 are formed on sidewalls of the polysilicon gate electrode. Thereafter, source/drain regions 6 are formed by ion implantation, where the polysilicon gate electrode and the sidewall insulating films 4 are used as a mask. Thereafter, a refractory metal film is deposited on the semiconductor substrate 1, covering the polysilicon gate electrode, and then by annealing, the polysilicon gate electrode is fully silicided to form a FUSI gate electrode 3a while silicide layers 7a are formed in surface portions of the source/drain regions 6.
A process with a stress control may be employed so as to improve transistor performance. As an example of such a technique, a conventional method in which a liner nitride film is utilized will be described with reference to FIG. 33 (see Japanese Unexamined Patent Application Publication No. 2007-049166 (particularly, FIG. 1B)). Initially, a polysilicon gate electrode 13 is formed on an active region surrounded by an STI region 12 in a silicon substrate 11, and thereafter, sidewall spacers (not shown) are formed on both sides of the polysilicon gate electrode 13 with offset spacers 14 and oxide layers 15 interposed therebetween. Next, a pair of source/drain regions 17 is formed in portions of the silicon substrate 11 on both sides of the polysilicon gate electrode 13 by ion implantation, where the polysilicon gate electrode 13, the offset spacers 14, and the sidewall spacers are used as a mask. Next, silicide layers 18 are formed in upper portions of the polysilicon gate electrode 13 and the source/drain regions 17, and thereafter, the sidewall spacers are removed. Thereafter, a stress liner nitride film 19 is formed, covering the polysilicon gate electrode 13.